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preliminary datasheet versaclock ? low power cl ock generator IDT5P49EE801 idt? versaclock ? low power clock generator 1 IDT5P49EE801 rev c 061810 description the IDT5P49EE801 is a programmable clock generator intended for low power, battery operated consumer applications. there are four internal plls, each individually programmable, allowing for up to eight differrent output frequencies. the frequencies are generated from a single reference clock. the reference clock can come from either a tcxo or fundamental mode crystal. an additional 32khz crystal oscillator is available to provide a real time clock or non-critical performance mhz processor clock. the IDT5P49EE801 can be programmed through the use of the i 2 c interfaces. the programming interface enables the device to be programmed when it is in normal operation or what is commonly known as in system programmable. an internal eeprom allows t he user to save and restore the configuration of the device without having to reprogram it on power-up. each of the four plls has an 8-bit reference divider and a 11-bit feedback divider. this allows the user to generate four unique non-integer-related frequencies. the pll loop bandwidth is programmable to allow the user to tailor the pll response to the application. for instance, the user can tune the pll parameters to minimize jitter generation or to maximize jitter attenuation. spread spectrum generation is supported on one of the plls. the device is specifically designed to work with display applications to ensure that the spread profile remains consistent for each hsync in order to reduce row noise. it also may operate in standard spread sepctrum mode. there are total six 8-bit output dividers. one output bank can be configured to support lvttl or lvds. all other outputs are always set to lvttl. the outputs are connected to the plls via the switch matrix. the switch matrix allows the user to route the pll outputs to any output bank. this feature can be used to simplify and optimize the board layout. in addition, each output's slew rate and enable/disable function can be programmed. target applications ? smart mobile handset ? personal navigation device (pnd) ? camcorder ? dsc ? portable game console ? personal media player features ? four internal plls ? internal non-volatile eeprom ? internal i 2 c eeprom master interface ? fast (400khz) mode i 2 c serial interfaces ? input frequencies ? tcxo: 10 mhz to 40 mhz ? crystal: 8 mhz to 30 mhz ? rtc crystal: 32.768 khz ? output frequency ranges: khz to 120 mhz ? each pll has an 8-bit reference divider and a 11-bit feedback-divider ? 8-bit output-divider blocks ? one of the plls support spread spectrum generation capable of configuration to pixel rate, with adjustable modulation rate and amplitude to support video clock with no visible artifacts ? i/o standards: ? outputs - 1.8v/2.5v/3.3 v lvttl/ lvcmos ? outputs - 1 pair selectable 3.3 v lvds ? 3 independent adjustable vddo groups. ? programmable slew rate control ? programmable loop bandwidth settings ? programmable output inversion to reduce bimodal jitter ? individual output enable/disable ? power-down/sleep mode ? 10 ? a max in power down mode ? 32khz clock output active sleep mode ? 100 ? a max in sleep mode ? 1.8v vdd core voltage ? available in 28 pin 4x4mm qfn packages ? -40 to +85 c industrial temp operation
IDT5P49EE801 versaclock ? low power clock generator eeprom clock generator idt? versaclock ? low power clock generator 2 IDT5P49EE801 rev c 061810 functional block diagram note : out6a & out6b pair can be configured to be lvds or two single-ended lvttl outputs. plla pllb(ss) pllc plld xin/ref xout sda scl sel[1:0] refsel0 refsel2 control logic 32kxin 32kxout refsel1 refsel3 gnd vdd vddo2 vddo1 vddo3 /div6 out6a out6b /div4 out4 s r c 4 /div3 out3 s r c 3 /div2 out2 s r c 2 /div1 out1 s r c 1 /div0 out0 s r c 0 /div5 out5 s r c 5 s r c 6
IDT5P49EE801 versaclock ? low power clock generator eeprom clock generator idt? versaclock ? low power clock generator 3 IDT5P49EE801 rev c 061810 pin assignment pin descriptions pin name pin # i/o pin type pin description out5 1 o adjustable configurable clock output 5. single-ended output voltage levels are register controlled by ei ther vddo1, vddo2 or vddo3. out4 2 o adjustable configurable clock output 4. single-ended output voltage levels are register controlled by ei ther vddo1, vddo2 or vddo3. out3 3 o adjustable configurable clock output 3. single-ended output voltage levels are register controlled by ei ther vddo1, vddo2 or vddo3. sel0 4 i lvttl configuration se lect pin. weak internal pull down resistor. vddo1 5 power device power supply. connect to 1.8 to 3.3v. using register settings, select output voltage levels for out0-out6. vddo1 must be greater than or equal to both vddo2 and vddo3. x132k 6 i lvttl 32khz crystal_in -- reference crystal input x232k 7 o lvttl 32khz crystal_out -- reference crystal feedback. vddx 8 power crystal oscillator power supp ly. connect to 1.8v. use filtered analog power supply if available. gnd 9 power connect to ground. gnd 10 power connect to ground. vdd 11 power device power supply. connect to 1.8v. vddo2 12 power device power supply. connect to 1.8 to 3.3v. using register settings, select output volt age levels for out0-out6. 28 pin vfqfpn (top view) 16 out2 15 vddo2 11 sel1 14 vdd 13 gnd 12 10 gnd 9 vddx 17 xin/ref 18 out1 20 vdd 21 out0 22 vddo3 sclk 23 24 out6b vdd 19 25 out6a sda 26 27 vdd 28 vdd xout gnd 1 out5 2 out4 4 sel0 3 out3 5 vddo1 x1_32 6 7 x2_32 8
IDT5P49EE801 versaclock ? low power clock generator eeprom clock generator idt? versaclock ? low power clock generator 4 IDT5P49EE801 rev c 061810 note 1: outputs are user programmable to drive single-ended 1.8v/2.5v/3.3v lvttl. alway completely power up vdd and vddx prior to applying vddo power. always power up device into ?active? configuration modes, prior to asserting power down/sleep mode sel=00. note 2: default configuration clk4=buffered mhz reference output and clk2=buffered 32.768khz output. all other outputs are off. out2 13 o adjustable configurable clock output 2. single-ended output voltage levels are register controlled by ei ther vddo1, vddo2 or vddo3. sel1 14 i lvttl configuration select pin. weak internal pull down resistor. out1 15 o adjustable configurable clock output 1. single-ended output voltage levels are register controlled by ei ther vddo1, vddo2 or vddo3. vdd 16 power device power supply. connect to 1.8v. vdd 17 power device power supply. connect to 1.8v. out0 18 o adjustable configurable clock output 0. single-ended output voltage levels are register controlled by ei ther vddo1, vddo2 or vddo3. vddo3 19 power device power supply. connect to 1.8 to 3.3v. using register settings, select output volt age levels forout0-out6. sclk 20 i lvttl i 2 c clock. out6b 21 o adjustable configurable clock outpu t 6b. output voltage level is controlled by vddo1. out6a 22 o adjustable configurable clock outpu t 6b. output voltage level is controlled by vddo1. sda 23 i/o open drain bidirectional i 2 c data. vdd 24 power device power supply. connect to 1.8v. vdd 25 power device power supply. connect to 1.8v. gnd 26 power connect to ground. xin/ ref 27 i lvttl mhz crystal_in -- reference crystal input or external reference clock input. xout 28 o lvttl mhz crystal_out -- reference crystal feedback. ep -- exposed thermal pad should be externally connected to ground. pin name pin # i/o pin type pin description
IDT5P49EE801 versaclock ? low power clock generator eeprom clock generator idt? versaclock ? low power clock generator 5 IDT5P49EE801 rev c 061810 pll features and descriptions pll block diagram crystal input (xin/ref) the crystal oscillators should be fundamental mode quartz crystals; overtone crystals are not suitable. crystal frequency should be specified for parallel resonance with 50 ? maximum equivalent series resonance. crystal load capacitors the device crystal connections should include pads for small capacitors from x1 to ground and from x2 to ground. these capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short pcb traces (and no vias) between the crystal and device. crystal capacitors must be connected from each of the pins x1 and x2 to ground. the crystal cpacitors are internal to the device and have an effective value of 8pf. reference pre-divider, reference divider, feedback-divider and post-divider each pll incorporates an 8-bit reference-scaler and a 11-bit feedback divider which allows the user to generate four unique non-integer-related frequencies. plla and plld each have a feedback pre-divider that provides additional multiplication for khz reference clock applications. each output divider supports 8-bit post-divider. the following equation governs how the output frequency is calculated. where f in is the reference frequency, a is the feedback pre-divider value, m is the feed back-divider value, d is the reference divider value, odiv is the total post-divider value, and f out is the resulting output frequency. programming any of the dividers may cause glitches on the outputs. vco 11-bit 8-bit d m a 1-bit ref-divider (d) values feedback pre-divider (xdiv) values feedback (m) values programmable loop bandwidth spread spectrum generation capability plla 1 - 255 1 or 4 1 6 - 2047 yes no pllb 1 - 255 4 6 - 2047 yes yes pllc 1 - 255 1 or 8 bit divide 2 6 - 2047 yes no plld 1 - 255 1 or 4 1 6 - 2047 yes no 1.xdiva or xdivd=0, a=1. xdiva or xdivd=1, a=4. 2.xdivc =0, a=1. xdivc=1 turns on 8 bit predivide multiplier, a=fbc2[7:0]. total feedback divide equals fbc[10:0] *fbc2[7:0]. f out = a*m d ( ) f in * odiv (eq. 2)
IDT5P49EE801 versaclock ? low power clock generator eeprom clock generator idt? versaclock ? low power clock generator 6 IDT5P49EE801 rev c 061810 spread spectru m generation (pllb) pllb has spread spectrum g eneration capability, which users have the option of turning on and off. spread spectrum profile, frequency, and spread are fully programmable (within limits). the programmable spread spectrum generation parameters are nc[10:0], mod[12:0], and nss[10:0] bits. to enable spread spectrum, set ssenb_b=0. the spread spectrum circuitry was specifically developed to accommodate video display applications. the spread modulation frequency can be defined to exactly equal the horizontal line frequency (hsync) nc[10:0] these bits are used to determine the number of pulses per spread spectrum cycle. for video applications, nc is the number of pixels on the horizontal display row (or integer multiple of displayed pixels in a row). by matching the spread period to the screen, no tearing or ?shimmer? will be apparent. nc must be an even number to insure that the upward spread transition has the same number of steps as the downward spread transition. for non-video applications, this can also be seen as the number of clock cycles for a complete spread spectrum period. mod[12:0] these bits relate the vco frequency to the target average spread output frequency (f mid ). f mid = (f vco ) / 8 f max = f mid + (ss% * f mid) f min = f mid - (ss% * f mid) mod = (f ref * nc) / (2 * f mid ) nss[10:0] these bits control the amplitude of the spread modulation. nss = (nc / 2) + (nc / 8) * (f max - f min ) / f mid modulation frequency: f mod = f mid / nc (eq. 11) video example f ref = 27 mhz, f out = 27 mhz, 640 pixels per line, center spread of 1%. using f vco =432mhz, find the necessary spread spectrum register settings. f mid = f vco /8 nc = 640 (integer number of spread periods/screen) mod = (25mhz * 640)/(2 * 54mhz) = 160 nss = (640/2)+(640/8)*(27.27mhz-26.73mhz)/27mhz = 321. f mod = 27mhz/640 = 11.8khz. non-video example f ref = 25mhz, f out = 27 mhz, 31.25khz modulation rate, center spread of 1%. find the necessary spread spectrum register settings. f mid = f vco / 8 f mod = 31.25khz = 50.625mhz/nc. nc = 1620 mod = (25mhz * 1620)/(2 * 50.625mhz) = 400 nss = (1620/2)+(1620/8)*(27.27mhz-26.73mhz)/27mhz = 814.
IDT5P49EE801 versaclock ? low power clock generator eeprom clock generator idt? versaclock ? low power clock generator 7 IDT5P49EE801 rev c 061810 vsync, hsync, dot_clk ? mo dulation rate relationship loop filter the loop filter for each pll can be programmed to optimize the jitter performance. the low-pass frequency response of the pll is the mechanism that dictates the jitter transfer characteristics. the loop bandwidth can be extracted from the jitter transfer. a narrow loop bandwidth is good for jitter attenuation while a wide loop ban dwidth is best for low jitter generation. the specific loop filter components that can be programmed are the resistor via the rz[4:0] bits, zero capacitor via the cz[2:0] bits, pole capacitor via the cp[1:0] bits, and the charge pump current via the ip#[2:0] bits. the following equations govern how the loop filter is set: zero capacitor (cz) = 280pf pole capacitor (cp) = 30pf charge pump (ip) = ip#[2:0] ua vco gain (k vco ) = 350mhz/v * 2 ? integer multiple of hsync periods vsync hsync dot_clk modulation rate x/2 x x/2 x x = number of cycles of dot_clk per hsync period. x/2 = number of cycles of dot_clk that the modulation edge rises/falls.
IDT5P49EE801 versaclock ? low power clock generator eeprom clock generator idt? versaclock ? low power clock generator 8 IDT5P49EE801 rev c 061810 pll loop bandwidth: charge pump gain (k ?? ) = ip / 2 ?? vco gain (k vco ) = 950mhz/v * 2 ? m = total multiplier value (see the pre-scalers, feedback-dividers, post-dividers section for more detail) ? c = (rz * k ?? * k vco * cz)/(m * (cz + cp)) fc = ? c / 2 ?? note, the phase/frequency detector frequency (f pfd ) is typically seven times the pll closed-loop bandwidth (fc) but too high of a ratio will redu ce your phase margin thus compromising loop stability. to determine if the loop is stable, the phase margin ( ? m) would need to be calculated as follows. phase margin: ? z = 1 / (rz * cz) ? p = (cz + cp)/(rz * cz * cp) ? m = (360 / 2 ? ) * [tan -1 ( ? c/ ? z) - tan -1 ( ? c/ ? p)] to ensure stability in the l oop, the phase margin is recommended to be > 60 but to o high will result in the lock time being excessively long. ce rtain loop filter parameters would need to be compromised to not only meet a required loop bandwidth but to also maintain lo op stability. example fc = 150khz is the desired loop bandwidth. the total a*m value is 160. the ? (damping factor) target should be 0.7, meaning the loop is critically damped. given fc and a*m, an optimal loop filter setting nee ds to be solved for that will meet both the pll loop bandwidth and maintain loop stability. choose a mid-range charge pump from register table icp= 11.9ua. k ?? * k vco = 300mhz/v * 40ua = 12000a/vs ? c = 2 ?? * fc = 9.42x10 5 s -1 ? p = (cz + cp)/(rz * cz * cp) = ? z (1 + cz / cp) solving for rz, the best possible value rz=30kohms (rz[1:0]=10) gives ? = 1.2 solving back for the pll loop bandwidth, fc=149khz. the phase margin must be checked for loop stability. ? m = (360 / 2 ? ) * [tan -1 (9.42x10 5 s -1 / 1.19x10 5 s -1 ) - tan -1 (9.42x10 5 s -1 / 1.23x10 6 s -1 )] = 45 the phase margin would be acceptable with a fairly stable loop.
IDT5P49EE801 versaclock ? low power clock generator eeprom clock generator idt? versaclock ? low power clock generator 9 IDT5P49EE801 rev c 061810 sel[1:0] function the IDT5P49EE801 can support up to three unique configurations. users may pre-programmed all these configurations, and select the configurations using sel[1:0] pins. alternatively, users may use i2c interface to configure these registers on- the-fly. always power up with sel1=1 and/or sel0=1. do not power up device into power down mode sel=00 . power down/sleep mode is selected by the no_pd bit. no_pd=0 enables power down mode with no outputs. no_pd=1 enables sleep mode with 32khz output on out4 configuration outx io standard users can configure the individual output io standard from a single 3.3v power supply. each output can support 1.8v/ 2.5v or 3.3v lvcmos. output pair out6a/out6b can be configured to support an lvds output. for lvds support, vddo1 must be set to 3.3v. vddo1 must have the highest voltage of any pin on the device. vddo2 and vddo3 may have any value between 1.8v and vddo1. programming the device i 2 c may be used to program the IDT5P49EE801. ? device (slave) address = 7'b1101010 i 2 c programming the IDT5P49EE801 is programmed through an i2c-bus serial interface, and is an i2c slave device. the read and write transfer formats are supported. the first byte of data after a write frame to the correct slave address is interpreted as the register address; this address auto-increments after each byte written or read. the frame formats are shown in the following illustration. framing sel1 sel0 configuration selections 0 0 power down/sleep mode 0 1 select config0 1 0 select config1 1 1 select config2
IDT5P49EE801 versaclock ? low power clock generator eeprom clock generator idt? versaclock ? low power clock generator 10 IDT5P49EE801 rev c 061810 first byte transmitted on i 2 c bus external i 2 c interface condition eeprom interface the IDT5P49EE801 can store its configuration in an internal eeprom. the conten ts of the device's internal programming registers can be saved to the eeprom by issuing a save instruction (progsave) and can be loaded back to the internal programming registers by issuing a restore instruction (progrestore). to initiate a save or restore using i 2 c, only two bytes are transferred. the device address is issued with the read/write bit set to ?0?, followed by the appropriate command code. the save or restore instruction executes after the stop condition is issued by the master, during which time the idt5p49 ee801 will not generate acknowledge bits. the IDT5P49EE801 will acknowledge the instructions after it has completed execution of them. during that time, the i 2 c bus should be interpreted as busy by all other users of the bus. on power-up of the IDT5P49EE801, an automatic restore is performed to load the eeprom co ntents into the internal programming registers. the id t5p49ee801 will be ready to accept a programming instruction once it acknowledges its 7-bit i 2 c address. progwrite progwrite command frame writes can continue as long as a stop condition is not sent and each byte will increment the register address.
IDT5P49EE801 versaclock ? low power clock generator eeprom clock generator idt? versaclock ? low power clock generator 11 IDT5P49EE801 rev c 061810 progread note: if the expected read command is not from the next higher register to the previous read or write command, then set a known ?read? register address prior to a read operation by issuing the following command: prior to progread command set register address the user can ignore the stop condition above and use a repeated start condition instead, straight after the slave acknowledgement bit (i.e., followed by the progread command): progread command frame progsave note: progwrite is for writing to the IDT5P49EE801 registers. progread is for reading the IDT5P49EE801 registers. progsave is for saving all the contents of the IDT5P49EE801 regist ers to the eeprom. progrestore is for loading the entire eeprom contents to the IDT5P49EE801 registers. progrestore during progrestore, output s will be turned off to ensure that no improper voltage levels are experienced before initialization.
IDT5P49EE801 versaclock ? low power clock generator eeprom clock generator idt? versaclock ? low power clock generator 12 IDT5P49EE801 rev c 061810 i 2 c bus dc characteristics i 2 c bus ac characterist ics for standard mode 1) no activity is allowed on i 2 c lines until vdd>1.62v. 2) a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ih min of the sclk signal) to bridge the undefined region of the falling edge of sclk. symbol parameter conditions min typ max unit v ih input high level 0.7xvdd 5.5 v v il input low level 0.3xvdd v v hys hysteresis of inputs 0.05xvdd v i in input leakage current v dd = 0v 1.0 a v ol output low voltage i ol = 3 ma 0.4 v symbol parameter min typ max unit f sclk serial clock frequency (scl) 0 100 khz t buf bus free time between stop and start 4.7 s t su:start setup time, start 4.7 s t hd:start hold time, start 4 s t su:data setup time, data input (sda) 250 ns t hd:data hold time, data input (sda) 1 0s t ovd output data valid from clock 3.45 s c b capacitive load for each bus line 400 pf t r rise time, data and clock (sda, sclk) 1000 ns t f fall time, data and clock (sda, sclk) 300 ns t high high time, clock (sclk) 4 s t low low time, clock (sclk) 4.7 s t su:stop setup time, stop 4 s
IDT5P49EE801 versaclock ? low power clock generator eeprom clock generator idt? versaclock ? low power clock generator 13 IDT5P49EE801 rev c 061810 i 2 c bus ac characteri stics for fast mode 1) no activity is allowed on i 2 c lines until vdd>1.62v. 2) a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ih min of the sclk signal) to bridge the undefined region of the falling edge of sclk. symbol parameter min typ max unit f sclk serial clock frequency (scl) 0 400 khz t buf bus free time between stop and start 1.3 s t su:start setup time, start 0.6 s t hd:start hold time, start 0.6 s t su:data setup time, data input (sda) 100 ns t hd:data hold time, data input (sda) 1 0s t ovd output data valid from clock 0.9 s c b capacitive load for each bus line 400 pf t r rise time, data and clock (sda, scl) 20 + 0.1xc b 300 ns t f fall time, data and clock (sda, scl) 20 + 0.1xc b 300 ns t high high time, clock (scl) 0.6 s t low low time, clock (scl) 1.3 s t su:stop setup time, stop 0.6 s
IDT5P49EE801 versaclock ? low power clock generator eeprom clock generator idt? versaclock ? low power clock generator 14 IDT5P49EE801 rev c 061810 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the IDT5P49EE801. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for ex tended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions capacitance symbol description max unit v dd internal power supply voltage -0.5 to +4.6 v v i input voltage -0.5 to +4.6 v v o output voltage (not to exceed 4.6 v) -0.5 to v dd +0.5 v t j junction temperature 150 c t stg storage temperature -65 to +150 c symbol parameter min typ max unit v dd power supply voltage for vdd closest to lvttl and core 1.62 1.8 1.98 v power supply voltage for vdd closest to lvds outputs 3.135 3.3 3.465 t a operating temperature, ambient -40 +85 c c load_out maximum load capacitance (3.3v lvttl only) 15 pf c load_out maximum load capacitance (1.8v or 2.5v lvttl only) 8 pf f in external reference crystal 8 30 mhz external reference clock clkin 1 40 t pu power up time for all v dd s to reach minimum specified voltage (power ramps must be monotonic) 0.05 5 ms symbol parameter min typ max unit c in input capacitance 3 pf crystal specifications xtal_freq crystal frequency 8 30 mhz xtal_min minimum crystal load capacitance tbd pf xtal_max maximum crystal load capacitance 35.4 pf xtal_v pp voltage swing (peak-to-peak, nominal) 1.5 2.3 3.2 v
IDT5P49EE801 versaclock ? low power clock generator eeprom clock generator idt? versaclock ? low power clock generator 15 IDT5P49EE801 rev c 061810 dc electrical characteristics for 3.3 volt lvttl 1 dc electrical characteristics for 2.5volt lvttl 1 dc electrical characteristics for 1.8volt lvttl 1 power supply characteri stics for lvttl outputs note 1: see ?recommended operating conditions? table. alway completely power up vdd and vddx prior to applying vddo power. symbol parameter test conditions min typ max unit v oh output high voltage i oh = 33ma 2.4 vddo v v ol output low voltage i oh = 33ma 0.4 v v ih input high voltage 2 v v il input low voltage 0.8 v i ozdd output leakage current 3-state outputs 5 a symbol parameter test conditions min typ max unit v oh output high voltage i oh = 25ma 2.1 vddo v v ol output low voltage i oh = 25ma 0.4 v i ozdd output leakage current 3-state outputs 5 a symbol parameter test conditions min typ max unit v oh output high voltage i oh = 18ma 0.65*vddo vddo v v ol output low voltage i oh = 18ma 0.35*vddo v i ozdd output leakage current 3-state outputs 5 a symbol parameter test conditions typ max unit i tot total power vdd supply current f reference clock = 25 mhz, c l = 7 pf tbd ma
IDT5P49EE801 versaclock ? low power clock generator eeprom clock generator idt? versaclock ? low power clock generator 16 IDT5P49EE801 rev c 061810 dc electrical characteristics for lvds power supply characteri stics for lvds outputs 1 note 1: out6a and out6b are toggling. other outputs are powered down. note 2: the termination resistors are excluded from these measurements. ac timing electrical characteristics (spread spectrum generation = off) symbol parameter min typ max unit v ot (+) differential output voltage fo r the true binary state 247 454 mv v ot (-) differential output voltage for the false binary state -247 -454 mv v ot change in v ot between complimentary output states 50 mv v os output common mode voltage (offset voltage) 1.125 1.2 1.375 v v os change in v os between complimentary output states 50 mv i os outputs short circuit current, v out + or v out - = 0v or vdd tbd tbd ma i osd differential outputs shor t circuit current, v out + = v out -tbdtbdma symbol parameter test conditions 2 typ max unit i ddq quiescent vdd power supply current ref = low outputs enabled, all outputs unloaded tbd tbd ma i ddd dynamic vdd power supply current per output vdd = max., c l = 0pf tbd tbd a/mhz i tot total power vdd supply current f reference clock = 25 mhz, c l = 5 pf tbd tbd ma symbol parameter test conditions min. typ. max. units f in input frequency input frequency limit (clkin) 1 1 40 mhz 1 / t1 output frequency single ended clock output limit (lvttl) 3.3v 0.001 120 mhz single ended clock output limit (lvttl) 2.5v 110 mhz single ended clock output limit (lvttl) 1.8v 100 mhz differential clock output limit (lvds) 150 mhz f vco vco frequency vco operating frequency range 100 475 mhz f pfd pfd frequency pfd operating frequency range 0.50 20 mhz t2 input duty cycle duty cycle for input 40 60 % t3 output duty cycle measured at vdd/2 45 55 %
IDT5P49EE801 versaclock ? low power clock generator eeprom clock generator idt? versaclock ? low power clock generator 17 IDT5P49EE801 rev c 061810 spread spectrum genera tion specifications note 1: practical lower frequency is determined by loop filter settings. t4 slew rate, slewx(bits) = 00 single-ended 3.3v lvcmos output clock rise and fall time, 20% to 80% of vdd (output load = 7 pf) 3.5 v/ns slew rate, slewx(bits) = 01 single-ended 3.3v lvcmos output clock rise and fall time, 20% to 80% of vdd (output load = 7 pf) 2.75 slew rate, slewx(bits) = 10 single-ended 3.3v lvcmos output clock rise and fall time, 20% to 80% of vdd (output load = 7 pf) 2 slew rate, slewx(bits) = 11 single-ended 3.3v lvcmos output clock rise and fall time, 20% to 80% of vdd (output load = 7 pf) 1.25 t5 rise times lvds, 20% to 80% 600 ps fall times 600 t7 clock jitter peak-to-peak period jitter, clk outputs measured at vdd/2; f pfd >= 10 mhz single output frequency only. 100 ps peak-to-peak period jitter, clk outputs measured at vdd/2; f pfd >= 10 mhz multiple output frequencies switching. 200 ps t6 output skew skew between out6 and out6b outputs. 200 ps t7 lock time pll lock time from power-up (using mhz reference clock) 2 520ms pll lock time from power-up using 32.768khz reference clock) 13 s pll lock time from shutdown mode 2 ms 1.input clock (square wave) may be used at 1 mhz. 2.time from supply voltage crosses vdd=1.62v to plls are locked. symbol parameter description min typ max unit f in input frequency input frequency limit 1 1 40 mhz f mod mod frequency modulation frequency 32 120 khz f spread spread value amount of spread value (programmable) - down spread programmable %f out amount of spread value (programmable) - center spread programmable symbol parameter test conditions min. typ. max. units
IDT5P49EE801 versaclock ? low power clock generator eeprom clock generator idt? versaclock ? low power clock generator 18 IDT5P49EE801 rev c 061810 test circuits and conditions 1 test circuits for dc outputs other termination scheme (block diagram) lvttl: ~7pf for each output lvds: 100 ? between differential outputs with 5pf
IDT5P49EE801 versaclock ? low power clock generator eeprom clock generator idt? versaclock ? low power clock generator 19 IDT5P49EE801 rev c 061810 programming registers table addr default register hex value bit # description 7654321 0 0x00 00 onxtalb csx2[1:0] csx1[1:0] xtal32onb reserved onxtalb - mhz crystal active low csx2 [1:0]- internal 32khz crystal cap2 00 - 18pf; 10 - 30pf 01 - 24pf; 11 - 36pf csx1 [1:0] - internal 32khz crystal cap1 00 - 0pf; 10 - 6pf 01 - 3pf; 11 - 9pf xtal32onb - 32k crystal active low 0x01 00 inv[0] slew0[0:1] no_pd ps0[2:1] reserved no_pd - enables/disables 32khz clock output on config 00. no_pd=0 - 32khz is off. no_pd=1 - 32khz remains active. 32khz output must be on out4 inv[#] - invert output# slew#[0:1] - output# slew setting 0 0 - 5.1v/ns 0 1 - 4.4v/ns 1 0 - 2.8v/ns 1 1 - 1.8v/ns ps#[2:1] -power select 00 - reserved 01 - clk# connects to vddo1 10 - clk# connects to vddo2 11 - clk# connects to vddo3 0x02 00 reserved 0x03 00 inv[1] slew1[0:1] reserved ps12:1] reserved 0x04 00 inv[2] slew20:1] reserved ps2[2:1] reserved 0x05 00 reserved 0x06 00 inv[3] slew3[0:1] reserved ps3[2:1] reserved 0x07 00 inv[4] slew4[0:1] reserved ps42:1] reserved 0x08 00 inv[5] slew5[0:1] reserved ps5[2:1] reserved 0x09 00 inv[6b] inv[6] slew6[0:1] reserved 0x0a 00 reserved 0x0b 00 reserved 0x0c 00 reserved 0x0d 00 reserved 0x0e 00 refa[7:0] configuration0 refa[7:0] - reference divide plla 0x0f 00 fba[10:3) fba[10:0] - feedback divide plla 0x10 00 reserved fba[2:0) 0x11 00 reserved xdiva rza[1:0] ipa[2:0] refsela xdiva - fb predivide plla; 0 - /1; 1 - /4 rza[1:0] - zero resistor plla 00 - 5kohm 01 - 10kohm 10 - 30kohm 11 - 80kohm ipa[2:0] - charge pump current plla 100 - 6.3ua 101 -11.9 ua 110 - 17.7 ua 111 - 22.7ua refsela - clock input plla 0 - mhz input 1 - 32khz input 0x12 00 refb[7:0] refb[7:0] - reference divide pllb 0x13 00 fbb[10:3] fbb[10:0] - feedback divide pllb 0x14 00 mod[4:0] fbb[2:0] pllb spread parameters mod[12:0] nc[10:0] nss[12:0] 0x15 00 mod[12:5] 0x16 00 nc[10:3] 0x17 00 nss[4:0] nc[2:0] 0x18 00 nss[12:5]
IDT5P49EE801 versaclock ? low power clock generator eeprom clock generator idt? versaclock ? low power clock generator 20 IDT5P49EE801 rev c 061810 0x19 20 reserved ipb[2:0] rzb[1:0] rzb[1:0] - zero resistor pllb 00 - 5kohm 01 - 10kohm 10 - 30kohm 11 - 80kohm ipb[2:0] - charge pump current pllb 000 - 0.37ua, 100 - 6.3ua 001 - 1.1ua, 101 - 11.9ua 010 - 1.8 ua, 110 - 17.7ua 011 - 3.4ua, 111 - 22.7ua refselb - clock input pllb 0 - mhz input 1 - 32khz input 0x1a 00 reserved refselb ssenb_b 0x1b 00 refc[7:0] refc[7:0] - reference divide pllc 0x1c 00 fbc[10:3] fbc[10:0] - feedback divide pllc 0x1d 00 reserved fbc[2:0] 0x1e 00 fbc2[7:0] fbc2 - feedback predivide pllc turn on using xdivc=1 0x1f 00 ipc[2:0] rzc[1:0] reserved xdivc refselc rzc[1:0] - zero resistor pllc 00 - 5kohm 01 - 10kohm 10 - 30kohm 11 - 80kohm ipc[2:0] - charge pump current pllc 100 - 6.3ua 101 -11.9 ua 110 - 17.7 ua 111 - 22.7ua refselc 0 - mhz input 1 - 32khz input 0x20 00 refd[7:0] refd[7:0] - reference divide plld 0x21 00 fbd[10:3] fbd[10:0] - feedback divide plld 0x22 00 reserved fbd[2:0] 0x23 00 xdivd rzd[1:0] ipd[2:0] refseld[1:0] xdivd - fb predivide plld; 0 - /1; 1 - /4 rzd[1:0] - zero resistor plld 00 - 5kohm 01 - 10kohm 10 - 30kohm 11 - 80kohm ipd[2:0] - charge pump current plld 100 - 6.3ua 101 -11.9 ua 110 - 17.7 ua 111 - 22.7ua refseld[1:0] 00 - mhz input 11 - 32khz input others - reserved 0x24 00 od0[7:0] od#[7:0] - output divide# 0x25 00 reserved 0x26 00 od1[7:0] 0x27 00 od2[7:0] 0x28 00 reserved 0x29 00 od3[7:0] 0x2a 00 od4[7:0] 0x2b 00 od5[7:0] 0x2c 00 od6[7:0] addr default register hex value bit # description 7654321 0
IDT5P49EE801 versaclock ? low power clock generator eeprom clock generator idt? versaclock ? low power clock generator 21 IDT5P49EE801 rev c 061810 0x2d 00 scr6[1:0] scr5[1:0] scr4[1:0] scr3[1:0] src6[1:0] - od6 source 00 - off; 10 - pllc 01 - plla; 11 - mhz reference src5[1:0] - od5 source 00 - off; 10 - plla 01 - pllc; 11 - pllb src4[1:0] - od4 source 00 - off; 10 - mhz reference 01 - pllc; 11 - 32khz reference src3[1:0] - od3 source 00 - off; 10 - 32khz reference 01 - mhz reference; 11 - plld 0x2e 00 reserved scr2[1:0] scr1[1:0] reserved src2[1:0] - od2 source 00 - off; 10 - pllb 01 - 32khz reference; 11 - plld src1[1:0] - od1 source 00 - off; 10 - pllc 01 - plla; 11 - plld 0x2f 00 scr0[1:0] reserved src0[1:0] - od0 source 00 - off; 10 - pllc 01 - pllb; 11 - plld 0x30 00 reserved 0x31 00 pdb[6] lvds_on oe[6b] oe[6] reserved pdb[#] - powerdown out#. pdb[#]=0, out# driven low oe[#] - output enable out#. oe[#]=0, out# tri-stated. if pdb#=oe#=0, out# driven low lvds_on 0 - out6a/out6b lvcmos outputs 1 - out6a/out6b lvds outputs. vddo must be 3.3v 0x32 00 oe[5] oe[4] oe[3] reserved oe[2] oe[1] reserved oe[0] 0x33 00 pdb[5] pdb[4] pdb[3] reserved pdb[2] pdb[1] reserved pdb[0] 0x34 00 refa[7:0] configuration1 (see definitions from configuration0 above) 0x35 00 fba[10:3) 0x36 00 reserved fba[2:0) 0x37 00 reserved xdiva rza[1:0] ipa[2:0] refsela 0x38 00 refb[7:0] 0x39 00 fbb[10:3] 0x3a 00 mod[4:0] fbb[2:0] 0x3b 00 mod[12:5] 0x3c 00 nc[10:3] 0x3d 00 nss[4:0] nc[2:0] 0x3e 00 nss[12:5] 0x3f 40 reserved ipb[2:0] rzb[1:0] 0x40 00 reserved refselb ssenb_b 0x41 00 refc[7:0] 0x42 00 fbc[10:3] 0x43 00 reserved fbc[2:0] 0x44 00 fbc2[7:0] 0x45 00 ipc[2:0] rzc[1:0] reserved xdiv refselc 0x46 00 refd[7:0] 0x47 00 fbd[10:3] 0x48 00 reserved fbd[2:0] 0x49 00 xdivd rzd[1:0] ipd[2:0] refseld[1:0] 0x4a 00 od0[7:0] 0x4b 00 reserved 0x4c 00 od1[7:0] 0x4d 00 od2[7:0] 0x4e 00 reserved addr default register hex value bit # description 7654321 0
IDT5P49EE801 versaclock ? low power clock generator eeprom clock generator idt? versaclock ? low power clock generator 22 IDT5P49EE801 rev c 061810 0x4f 00 od3[7:0] 0x50 00 od4[7:0] 0x51 00 od5[7:0] 0x52 00 od6[7:0] 0x53 00 scr6[1:0] scr5[1:0] scr4[1:0] scr3[1:0] 0x54 00 reserved scr2[1:0] scr1[1:0] reserved 0x55 00 scr0[1:0] reserved 0x56 00 reserved 0x57 00 pdb[6] lvds_on oe[6b] oe[6] reserved 0x58 00 oe[5] oe[4] oe[3] reserved oe[2] oe[1] reserved oe[0] 0x59 00 pdb[5] pdb[4] pdb[3] reserved pdb[2] pdb[1] reserved pdb[0] 0x5a 00 refa[7:0] configuration2 (see definitions from configuration0 above) 0x5b 00 fba[10:3) 0x5c 00 reserved fba[2:0) 0x5d 00 reserved xdiva rza[1:0] ipa[2:0] refsela 0x5e 00 refb[7:0] 0x5f 00 fbb[10:3] 0x60 00 mod[4:0] fbb[2:0] 0x61 00 mod[12:5] 0x62 00 nc[10:3] 0x63 00 nss[4:0] nc[2:0] 0x64 00 nss[12:5] 0x65 40 reserved ipb[2:0] rzb[1:0] 0x66 00 reserved refselb ssenb_b 0x67 00 refc[7:0] 0x68 00 fbc[10:3] 0x69 00 reserved fbc[2:0] 0x6a 00 fbc2[7:0] 0x6b 00 ipc[2:0] rzc[1:0] reserved xdiv refselc 0x6c 00 refd[7:0] 0x6d 00 fbd[10:3] 0x6e 00 reserved fbd[2:0] 0x6f 00 xdivd rzd[1:0] ipd[2:0] refseld[1:0] 0x70 00 od0[7:0] 0x71 00 reserved 0x72 00 od1[7:0] 0x73 00 od2[7:0] 0x74 00 reserved 0x75 00 od3[7:0] 0x76 00 od4[7:0] 0x77 00 od5[7:0] 0x78 00 od6[7:0] 0x79 00 scr6[1:0] scr5[1:0] scr4[1:0] scr3[1:0] 0x7a 00 reserved scr2[1:0] scr1[1:0] reserved 0x7b 00 scr0[1:0] reserved 0x7c 00 reserved 0x7d 00 pdb[6] lvds_on oe[6b] oe[6] reserved 0x7e 00 oe[5] oe[4] oe[3] reserved oe[2] oe[1] reserved oe[0] 0x7f 00 pdb[5] pdb[4] pdb[3] reserved pdb[2] pdb[1] reserved pdb[0] addr default register hex value bit # description 7654321 0
IDT5P49EE801 versaclock ? low power clock generator eeprom clock generator idt? versaclock ? low power clock generator 23 IDT5P49EE801 rev c 061810 marking diagram (nl28) notes: 1. ?z? is the device step (1 to 2 characters). 2. yyww is the last two digits of the year and week that the part was assembled. 3. ?$? is the assembly mark code. 4. ?g? after the two-letter package code designates rohs compliant package. 5. ?i? at the end of part number indicates industrial temperature range. 6. bottom marking: country of origin if not usa. thermal characteristics 28-pin qfn 4801di #yyww$ parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ? ja still air 47.0 ? c/w ? ja 1 m/s air flow 41.8 ? c/w ? ja 2.5 m/s air flow 39.2 ? c/w thermal resistance junction to case ? jc 52.9 ? c/w
IDT5P49EE801 versaclock ? low power clock generator eeprom clock generator idt? versaclock ? low power clock generator 24 IDT5P49EE801 rev c 061810 package outline and package dimensions (28-pin 4mm x 4mm qfn) package dimensions are kept current with jedec publication no. 95 ordering information parts that are ordered with a ?g? after the two-letter pacakage code are the pb-fr ee configuration and are rohs compliant. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any paten ts or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are im plied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves th e right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. millimeters symbol min max a0.801.00 a1 0 0.05 a3 0.20 reference b0.150.25 e 0.40 basic n28 n d 7 n e 7 d x e basic 4.00 x 4.00 d2 2.50 2.70 e2 2.50 2.70 l0.300.50 part / order number marking shipping packaging package temperature 5p49ee801ndgi see page 23 tubes 28pin vfqfpn -40 to +85 ? c 5p49ee801ndgi8 see page 23 tape and reel 28pin vfqfpn -40 to +85 ? c sawn singulation 1 2 n e d index area top view seating plane a3 a1 c a l e2 e2 2 d2 d2 2 e c 0.08 (ref) n d & n e odd (ref) n d & n e even (n d -1)x (ref) e n 1 2 b thermal base (typ) if n d & n e are even (n e -1)x (ref) e e 2 ep ? exposed thermal pad should be externally connected to ground.
IDT5P49EE801 versaclock ? low power clock generator eeprom clock generator idt? versaclock ? low power clock generator 25 IDT5P49EE801 rev c 061810 revision history rev. originator date description of change -- r.willner 9/23/09 initial preliminary datasheet a r.willner 11/20/09 no_pd bit inclusion - 32khz clock on/off in config 00. b r.willner 3/25/10 typographical changes. correct spread spectrum calculations. c r.willner 6/18/10 typographical changes. default configuration.
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